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????????????????????????????????????????????????????????????????? maxim integrated products 1 19-6179; rev 0; 1/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX17598.related . general description the MAX17598/max17599 low i q , active clamp current- mode pwm controllers contain all the control circuitry required for the design of wide-input isolated/non-iso - lated forward-converter industrial power supplies. the MAX17598 is well-suited for universal input (rectified 85v ac to 265v ac) or telecom (36v dc to 72v dc) power supplies. the max17599 is optimized for low-voltage industrial supplies (4.5v dc to 36v dc). the devices include an aux driver that drives an aux - iliary mosfet (clamp switch) that helps implement the active-clamp transformer reset topology for forward con - verters. such a reset topology has several advantages including reduced voltage stress on the switches, trans - former size reduction due to larger allowable flux swing, and improved efficiency due to elimination of dissipative snubber circuitry. programmable dead time between the aux and main driver allows for zero voltage switching (zvs). the switching frequency is programmable from 100khz to 1mhz for the devices with an accuracy of q 5% using an external resistor. this allows the optimization of the magnetic and filter components, resulting in compact, cost-effective isolated/nonisolated power supplies. for emi-sensitive design, the ics incorporate a program - mable frequency dithering feature and enables low emi spread-spectrum operation. an input undervoltage lockout (en/uvlo) is provided for programming the input-supply start voltage, and to ensure proper operation during brownout conditions. the en/uvlo input is also used to turn on/off the ics. input overvoltage (ovi) protection scheme is provided to make sure that the regulator shuts down when the input supply exceeds its maximum allowed value. to control inrush current, the devices incorporate an ss pin to set the soft-start time for the regulator. power dis - sipation under fault conditions is minimized by a hiccup overcurrent protection (hiccup mode). a soft-stop feature provides safe discharging of the clamp capacitor when the device is turned off, and allows the controller to restart in a well-controlled manner. additionally, a negative current limit is provided in the current-sense circuitry, helping limit the clamp switch current under dynamic operating conditions. a sync feature is provided to synchronize multiple convert - ers to a common external clock in noise-sensitive applica - tions. overtemperature faults trigger a thermal shutdown for reliable protection of the device. the ics are available in a 16-pin, tqfn package with 0.5 mm lead spacing. benefits and features s active clamp, peak current-mode forward pwm controller s 20 f a startup current in uvlo s 4.5v to 36v input-supply operating range (max17599) s programmable input undervoltage lockout s programmable input overvoltage protection s programmable 100khz to 1mhz switching frequency s switching frequency synchronization s programmable frequency dithering for low emi spread-spectrum operation s programmable dead time s adjustable soft-start s programmable slope compensation s fast cycle-by-cycle peak-current-limit 40ns typical propagation delay s 70ns internal leading-edge current-sense blanking s hiccup mode output short-circuit protection s soft-stop for well-controlled clamp capacitor discharge s negative current limit to limit clamp-switch clamp capacitor and transformer reverse current s 3mm x 3mm, lead-free 16-pin tqfn applications telecom and datacom power supplies isolated battery chargers servers and embedded computing industrial power supplies MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v in = 12v (for MAX17598, bring v in up to 21v for startup), v cs = v dither = v fb = v ovi = v sgnd = v pgnd = 0v, v en = +2v, auxdrv = ndrv = ss = comp = slope = unconnected, r rt = 25k i , r dt = 10k i , c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 2) v in (max17599 only) ............................................ -0.3v to +40v v drv to sgnd (MAX17598 only) .............................................. -0.3v to +16v (max17599 only) ................................................ -0.3v to +6v en ............................................................... -0.3v to (v in + 0.3v) ndrv, auxdrv ...................................... -0.3v to (v drv + 0.3v) ovi, rt, dither, comp, ss, fb, slope, dt to sgnd .......................................... -0.3v to +6v cs to sgnd ............................................................ -0.8v to +6v pgnd to sgnd .................................................... -0.3v to +0.3v maximum input /output current (continuous) v in , ndrv, auxdrv .................................................... 100ma ndrv, auxdrv (pulsed for less than 100ns) ..................... 1a continuous power dissipation (t a = +70 n c) tqfn (derate 20.8mw/c above 70c) .................... 1666mw operating temperature range ........................ -40c to +125c maximum junction temperature ..................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................ +300c soldering temperature (reflow) ...................................... +260c tqfn junction-to-case thermal resistance ( q jc ) ................. 7c/w junction-to-ambient thermal resistance ( q ja ) .......... 48c/w package thermal characteristics (note 1) parameter symbol conditions min typ max units input supply (v in ) v in voltage range v in MAX17598 8 29 v max17599 4.5 36 v in bootstrap uvlo wakeup v in-uvr in rising MAX17598 18.5 20 21.5 v max17599 3.5 4 4.4 v in bootstrap uvlo shutdown level v in-uvf in falling MAX17598 6.5 7 7.5 v max17599 3.3 3.9 4.25 v in supply startup current (under uvlo) i in- startup v in < uvlo 20 32 f a v in supply shutdown current i in-sh v en = 0v 20 32 f a v in supply current i in-sw switching, f sw = 400khz (MAX17598) 2 ma switching, f sw =400khz (max17599) 2 v in clamp (inc) (for MAX17598 only) v in clamp voltage v inc en = sgnd, i in = 2ma sinking (note 3) 30 33 36 v enanble (en) en threshold v enr v en rising 1.16 1.21 1.26 v v enf v en falling 1.1 1.15 1.20 en input leakage current i en v en = 1.5v, t a = +25 n c -100 +100 na
????????????????????????????????????????????????????????????????? maxim integrated products 3 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers electrical characteristics (continued) (v in = 12v (for MAX17598, bring v in up to 21v for startup), v cs = v dither = v fb = v ovi = v sgnd = v pgnd = 0v, v en = +2v, auxdrv = ndrv = ss = comp = slope = unconnected, r rt = 25k i , r dt = 10k i , c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 2) parameter symbol conditions min typ max units internal ldo (v drv ) v drv output voltage range v vdrv 8v < v in < 15v and 0ma < i vdrv < 50ma (MAX17598) 7.1 7.4 7.7 v 6v < v in < 15v and 0ma < i vdrv < 50ma (max17599) 4.7 4.9 5.1 v drv current limit i vdrv-max 70 100 ma v drv dropout v vdrv-do v in = 4.5v, i vdrv = 20ma (max17599) 4.2 v overvoltage protection (ovi) ovi overvoltage threshold v ovir v ovi rising 1.16 1.21 1.26 v v ovif v ovi falling 1.1 1.15 1.2 ovi masking delay t ovi-md 2 f s ovi input leakage current i ovi v ovi = 1v, t a = +25 n c -100 +100 na oscillator (rt) ndrv switching frequency range f sw 100 1000 khz ndrv switching frequency accuracy -8 +8 % maximum duty cycle d max f sw = 400khz, r dt = 10k i 71 72.5 74 % synchronization (dither/sync) synchronization logic-high input v ih-sync 3 v synchronization pulse width 50 ns synchronization frequency range f syncin 1.1 x f sw dithering ramp generator (dither/sync) charging current v dither = 0v 45 50 55 f a discharging current v dither = 2.2v 43 50 57 f a ramp-high trip point 2 v ramp-low trip point 0.4
????????????????????????????????????????????????????????????????? maxim integrated products 4 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers electrical characteristics (continued) (v in = 12v (for MAX17598, bring v in up to 21v for startup), v cs = v dither = v fb = v ovi = v sgnd = v pgnd = 0v, v en = +2v, auxdrv = ndrv = ss = comp = slope = unconnected, r rt = 25k i , r dt = 10k i , c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 2) parameter symbol conditions min typ max units soft-start/soft-stop (ss) soft-start charging current i ssch 9 10 11 f a soft-stop discharging current i ssdisch 4.4 5 5.6 f a ss bias voltage v ss 1.19 1.21 1.23 v ss discharge threshold v ssdisch soft-stop completion 0.15 v ndrv driver (ndrv) pulldown impedance r ndrv-n i ndrv (sinking) = 100ma 1.37 3 i pullup impedance r ndrv-p i ndrv (sourcing) = 50ma 4.26 8.5 i peak sink current c ndrv = 10nf 1.5 a peak source current c ndrv = 10nf 0.9 a fall time t ndrv-f c ndrv = 1nf 10 ns rise time t ndrv-r c ndrv = 1nf 20 ns auxdrv driver (auxdrv) pulldown impedance r auxdrv-n i auxdrv (sinking) = 100ma 3.35 7 i pullup impedance r auxdrv-p i auxdrv (sourcing) = 50ma 9.78 19 i peak sink current 0.7 a peak source current 0.3 a fall time t auxdrv-f c auxdrv = 1nf 16 ns rise time t auxdrv-r c auxdrv = 1nf 32 ns dead time (dt) ndrv to auxdrv delay (dead time) t dt ndrv $ to auxdrv $ r dt = 10k i 25 ns r dt = 100k i 250 auxdrv # to ndrv # r dt = 10k i 25 r dt = 100k i 250 current-limit comparator (cs) cycle-by-cycle peak- current-limit threshold v cs-peak 290 305 320 mv cycle-by-cycle runaway- current-limit threshold v cs-run 340 360 380 mv cycle-by-cycle reverse- current-limit threshold v cs-rev -122 -102 -82 mv
????????????????????????????????????????????????????????????????? maxim integrated products 5 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers electrical characteristics (continued) (v in = 12v (for MAX17598, bring v in up to 21v for startup), v cs = v dither = v fb = v ovi = v sgnd = v pgnd = 0v, v en = +2v, auxdrv = ndrv = ss = comp = slope = unconnected, r rt = 25k i , r dt = 10k i , c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 2) parameter symbol conditions min typ max units current-sense leading-edge blanking time t cs-blank from ndrv # edge 70 ns current-sense-blanking time for reverse-current limit t cs-blank- rev from auxdrv $ edge 70 ns propagation delay from comparator input to ndrv t pdcs from cs rising (10mv overdrive) to ndrv falling (excluding leading-edge blanking) 40 ns number of consecutive peak-current-limit events to hiccup n hiccup-p 8 event number of runaway current- limit events to hiccup n -hiccup-r 1 event overcurrent hiccup timeout 32,768 cycle minimum on-time t on-min 90 130 170 ns slope compensation (slope) slope bias current i slope 9 10 11 f a slope resistor range r slope 25 200 k i slope compensation ramp r slope = 100k : 140 165 190 mv/ f s default slope compensation ramp v slope < 0.2v or 4v < v slope 50 mv/ f s pwm comparator comparator offset voltage v pwm-os v comp - v cs 1.65 1.81 2 v current-sense gain a cs-pwm d comp/ d cs 1.75 1.97 2.15 v/v cs peak slope ramp current i cslope ramp current peak 13 20 f a comparator propagation delay t pwm change in v cs = 10mv (including internal lead-edge blanking) 110 ns error amplifier fb reference voltage v ref v fb , when i comp = 0v and v comp = 1.8v 1.19 1.21 1.23 v fb input bias current i fb v fb = 1.5v, t a = +25 n c -100 +100 na open-loop voltage gain a eamp 90 db transconductance gm 1.5 1.8 2.1 ms
????????????????????????????????????????????????????????????????? maxim integrated products 6 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers electrical characteristics (continued) (v in = 12v (for MAX17598, bring v in up to 21v for startup), v cs = v dither = v fb = v ovi = v sgnd = v pgnd = 0v, v en = +2v, auxdrv = ndrv = ss = comp = slope = unconnected, r rt = 25k i , r dt = 10k i , c vin = 1 f f, c vdrv = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted. typical values are at t a = t j = +25 n c.) (note 2) note 2: all devices are 100% production tested at +25 n c. limits over temperature are guaranteed by design. note 3: the MAX17598 is intended for use in universal input power supplies. the internal clamp circuit at in is used to prevent the bootstrap capacitor from changing to a voltage beyond the absolute maximum rating of the device when en is low (shut - down mode). externally limit the maximum current to in (hence to clamp) to 2ma (max) when en is low. typical operating characteristics (v in = 15v, v en/uvlo = +2v, comp = open, c vin = 1 f f, c vcc = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) parameter symbol conditions min typ max units transconductance bandwidth bw open-loop (gain = 1), -3db frequency 10 mhz source current v comp = 1.8v, v fb = 1v 80 120 210 f a sink current v comp = 1.8v, v fb = 1.75v 80 120 210 f a thermal shutdown thermal shutdown threshold temperature rising 160 c thermal shutdown hysteresis 20 c bootstrap uvlo wake-up level vs. temperature (MAX17598) MAX17598/9 toc01 temperature ( c) bootstrap uvlo wake-up level (v) 100 80 60 40 20 0 -20 19.99 20.00 20.01 20.02 20.03 20.04 19.98 -40 120 in wakeup level vs. temperature (max17599) MAX17598/9 toc02 temperature ( c) in wakeup level (v) 100 80 60 40 20 0 -20 3.95 4.00 4.05 4.10 4.15 3.90 -40 120 in uvlo shutdown level vs. temperature (MAX17598) MAX17598/9 toc03 temperature (c) in uvlo shutdown level (v) 100 80 60 40 20 0 -20 7.000 7.005 7.010 7.015 7.020 7.025 6.995 -40 120
????????????????????????????????????????????????????????????????? maxim integrated products 7 typical operating characteristics (continued) (v in = 15v, v en/uvlo = +2v, comp = open, c vin = 1 f f, c vcc = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) ndrv switching frequency vs. temperature MAX17598/9 toc07 temperature (c) ndrv switching frequency (khz) 100 80 40 60 0 20 -20 150 250 450 350 550 650 750 850 950 50 -40 120 r t = 10k i r t = 100k i frequency dithering vs. r dither MAX17598/9 toc08 r dither (ki) frequency dithering (%) 900 800 700 600 500 400 300 4 6 8 10 12 14 2 200 1000 dead time vs. r dt MAX17598/9 toc09 r dt (ki) dead time - dt (ns) 90 80 70 60 50 40 30 20 60 100 140 180 220 20 10 100 MAX17598/9 toc10 temperature (c) dead time (ns) dead time vs. temperature 244 246 248 250 252 242 120 100 80 60 40 20 0 -20 -40 r dt = 100ki peak-current-limit threshold vs. temperature MAX17598/9 toc11 temperature (c) peak-current-limit threshold (mv) 100 120 80 60 40 20 0 -20 301 302 303 304 305 306 307 300 -40 reverse current limit threshold vs. temperature MAX17598/9 toc12 temperature (c) reverse current limit threshold (mv) 120 100 60 80 0 20 40 -20 -103 -102 -101 -100 -99 -98 -97 -96 -95 -104 -40 in falling threshold vs. temperature (max17599) MAX17598/9 toc04 temperature (c) in uvlo shutdown threshold (v) 100 80 60 40 20 0 -20 3.80 3.85 3.90 3.95 4.00 3.75 -40 120 in supply current under uvlo vs. temperature MAX17598/9 toc05 temperature (c) in supply current under uvlo (a) 100 80 60 40 20 0 -20 20.5 21.5 22.5 23.5 24.5 25.5 19.5 -40 120 ndrv switching frequency vs. resistor MAX17598/9 toc06 frequency selection resistor (ki) ndrv switching frequency (khz) 95 85 65 75 25 35 45 55 15 100 200 300 400 500 600 700 800 900 1000 0 5 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers
????????????????????????????????????????????????????????????????? maxim integrated products 8 typical operating characteristics (continued) (v in = 15v, v en/uvlo = +2v, comp = open, c vin = 1 f f, c vcc = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) current-sense gain vs. temperature MAX17598/9 toc13 temperature (c) current-sense gain (v/v ) 100 120 80 60 40 20 0 -20 1.93 1.94 1.95 1.96 1.97 1.98 1.99 1.92 -40 fb regulation voltage vs. temperature MAX17598/9 toc14 temperature (c) fb regulation voltage (v) 100 80 60 40 20 0 -20 1.207 1.209 1.211 1.213 1.215 1.217 1.205 -40 120 enable startup waveform (duty cycle soft-start) MAX17598/9 toc15 v clampcap v en/uvlo 5v/div 5v/div 10v/div v out 2ms/div enable shutdown waveform (soft-stop) MAX17598/9 toc16 v clampcap v en/uvlo 5v/div 5v/div 10v/div v out 2ms/div soft-start from input MAX17598/9 toc17 v clampcap v in 10v/div 5v/div 25v/div v out 200ms/div input shutdown MAX17598/9 toc18 v clampcap v in 10v/div 5v/div 25v/div v out 20ms/div MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers
????????????????????????????????????????????????????????????????? maxim integrated products 9 typical operating characteristics (continued) (v in = 15v, v en/uvlo = +2v, comp = open, c vin = 1 f f, c vcc = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) ndrv and auxdrv signals (typ app circuit) MAX17598/9 toc19 v ndrv 5v/div v auxdrv 5v/div 1s/div ndrv peak source and sink currents MAX17598/9 toc21 i ndrv 0.7a /div 200ns/div peak sink current peak source current ss, ndrv, and auxdrv in hiccup mode MAX17598/9 toc23 v ndrv 5v/div v auxdrv 5v/div v ss 1v/div 4ms/div dead time between ndrv and auxdrv MAX17598/9 toc20 v ndrv 5v/div v auxdrv 5v/div 40ns/div 40ns auxdrv peak source and sink currents MAX17598/9 toc22 i auxdrv 0.28a /div 200ns/div peak sink current peak source current momentary ovi operation MAX17598/9 toc24 v ss 1v/div v out 5v/div v clamcap 25v/div v ovi 5v/div 2ms/div MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers
???????????????????????????????????????????????????????????????? maxim integrated products 10 typical operating characteristics (continued) (v in = 15v, v en/uvlo = +2v, comp = open, c vin = 1 f f, c vcc = 1 f f, t a = t j = -40 n c to +125 n c, unless otherwise noted.) load transient response (5v output) MAX17598/9 toc25 i load 500ma /div v out (ac) 100mv/div 1ms/div efficiency graph (5v output) MAX17598/9 toc26 load current (ma) efficiency (%) 1400 1200 800 1000 400 600 200 10 20 30 40 50 60 70 80 90 0 0 v dc = 24v bode plot (5v output and 24v input) MAX17598/98 toc27 gain 10db/div phase 24/div bw=19khz pm = 68 24 68 12 46 81 active clamp switching waveforms MAX17598/9 toc28 i primary 0.5a /div v ds 20v/div 1s/div MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers
???????????????????????????????????????????????????????????????? maxim integrated products 11 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers pin description pin configuration pin name function 1 dt dead-time programming resistor connection. connect resistor from dt to gnd to set the desired dead time between the ndrv and auxdrv signals. see the dead time section to calculate the resistor value for a particular dead time. 2 slope slope compensation programming input. a resistor rslope connected from slope to sgnd programs the amount of internal slope compensation. shorting this pin to sgnd sets a typical slope compensation of 50mv/ f s. 3 rt switching frequency programming resistor connection. connect resistor from rt to sgnd to set the pwm switching frequency. 4 dither/sync frequency dithering programming or synchronization connection. for spread-spectrum frequency operation, connect a capacitor from dither to sgnd and a resistor from dither to rt. to synchronize the internal oscillator to the externally applied frequency, connect dither/sync to the synchronization pulse. 5 comp transconductance amplifier output. connect the frequency compensation network between comp and sgnd. 6 fb transconductance error amplifier inverting input 7 ss soft-start/soft-stop capacitor pin for forward/flyback regulator. connect a capacitor from ss to sgnd to set the soft-start/soft-stop time interval. 8 sgnd signal ground. connect sgnd to the signal ground plane. 9 cs current-sense input. current-sense connection for average current-sense and cycle-by-cycle current limit. peak current limit trip voltage is 300mv. 10 pgnd power ground. connect pgnd to the power ground plane. 15 16 14 13 5 6 7 rt dither / syn c 8 dt pgnd cs auxdrv 13 v in 4 12 10 9 en/uvlo ovi sgnd ss fb comp slope ndrv 2 11 v drv ep tqfn MAX17598 max17599 top view +
???????????????????????????????????????????????????????????????? maxim integrated products 12 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers pin description (continued) detailed description the MAX17598/max17599 low i q active-clamp current- mode pwm controllers contain all the control circuitry required for the design of wide-input isolated/noniso - lated forward converter industrial power supplies. the MAX17598 has a rising uvlo threshold of 20v with a 13v hysteresis, and is therefore well-suited for universal input (rectified 85v ac to 265v ac) or telecom (36v dc to 72v dc) power supplies. the max17599 features a 4.1v ris - ing uvlo with a 200mv hysteresis and is optimized for low-voltage industrial supplies (4.5v dc to 36v dc). the devices include an aux driver that drives an auxiliary mosfet (clamp switch) that helps implement the active- clamp transformer reset topology for forward converters. such a reset topology has several advantages, including reduced voltage stress on the switches, transformer size reduction due to larger allowable flux swing, and improved efficiency due to elimination of dissipative snubber circuit - ry. programmable dead time between the aux and main driver allows for zero voltage switching (zvs). input voltage range the MAX17598 has different rising and falling undervolt - age lockout (uvlo) thresholds on the v in pin than those of the max17599. the thresholds for the MAX17598 are optimized for implementing power-supply startup schemes typically used for off-line ac/dc and telecom dc-dc power supplies that are typically encountered in electric industrial applications. as such, the MAX17598 has no limitation on the maximum input voltage, as long as the external components are rated suitably, and the maximum operating voltages of the MAX17598 are respected. the MAX17598 can be successfully used in universal input (85v to 265v ac) rectified bus applica - tions, rectified 3-phase dc bus applications, and tel - ecom (36v to 72v dc) applications. the v in pin of the max17599 has a maximum operating voltage of 36v. the max17599 implements rising and falling thresholds on the v in pin that assume power- supply startup schemes, typical of lower voltage dc-dc applications down to an input voltage of 4.5v dc. thus isolated/non-isolated active-clamp converters with sup - ply-voltage range of 4.5v to 36v can be implemented with the max17599. see the startup operation section for more details on power-supply startup schemes for the MAX17598/max17599. pin name function 11 ndrv external switching nmos gate-driver output 12 auxdrv pmos active-clamp-switch gate-driver output. auxdrv can also be used to drive a pulse transformer for synchronous flyback application. 13 v drv linear regulator output and driver input. connect a 2.2 f f bypass capacitor from v drv to pgnd as close as possible to the ic. 14 v in internal v drv regulator input. connect v in to the input voltage source. bypass v in to pgnd with a 1 f f minimum ceramic capacitor. 15 en/uvlo enable/undervoltage lockout pin. to externally program the uvlo threshold of the input supply, connect a resistive divider among input supply, en/uvlo, and sgnd. 16 ovi overvoltage comparator input. connect a resistive divider among the input supply, ovi, and sgnd to set the input overvoltage threshold. ep exposed pad
???????????????????????????????????????????????????????????????? maxim integrated products 13 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers figure 1. block diagram osc chipen/ hiccup 5v ldo pok en / uvlo ovi rt ss ss ss 1.21v 2v/0.4v v in uvlo 1.21v 1.21v -100mv 305mv 360mv ssdone hiccup v drv osc dither (sync) osc dither (sync) av ldo thermal sensor chipen ssdone control and driver logic dt v drv pgnd v drv pgnd driver driver 7.5v (MAX17598 ) or 5v (max17599 ) q 50a 5a 10a 10a 8 peakevent s or 1 runa wa y 1.21v reverse ilim comp peaklim comp runa wa y comp 360mv pw m comp 70ns blanking slop e decode current soft-start fixed or variable r r 1x MAX17598 max17599 auxdrv ndrv dead time auxdrv ndrv cs slope comp fb sgnd pgnd chipen
???????????????????????????????????????????????????????????????? maxim integrated products 14 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers figure 2. programming en/uvlo, ovi linear regulator (v drv ) the MAX17598/max17599 have an internal linear con - verter that is powered from the v in pin. the output of the linear regulator is connected to the v drv pin, and should be decoupled with a 2.2 f f capacitor to ground for sta - ble operation. the v drv converter output supplies the mosfet drivers internally to the MAX17598/max17599. the v drv voltage is regulated at 7.5v (typical) for the MAX17598, and at 5v (typical) for the max17599. the maximum operating voltage of the in pin is 29v for the MAX17598 and 36v for the max17599. maximum duty cycle (dmax) the MAX17598/max17599 operate at a maximum duty cycle of 70%. when the slope pin is connected to the v cc pin or left open, it has the necessary amount of slope compensation to provide stable, jitter-free current-mode control operation in applications where the operating duty cycle is less than 50%. slope compensa - tion is necessary for stable operation of current-mode controlled converters at duty cycles greater than 50%, in addition to the loop compensation required for small signal stability. the MAX17598/max17599 implement a slope pin for this purpose. see the slope compensation programming section for more details. applications information startup voltage and input overvoltage protection setting (en/uvlo, ovi) the en/uvlo pin in the MAX17598/max17599 serve as an enable/disable input, as well as an accurate program - mable undervoltage lockout (uvlo) pin. the MAX17598/ max17599 do not commence startup operations unless the en/uvlo pin voltage exceeds 1.21v (typical). the MAX17598/max17599 turn off if the en/uvlo pin voltage falls below 1.15v (typical). a resistor divider from the input dc bus to ground maybe used to divide down and apply a fraction of the input dc voltage to the en/uvlo pin as shown in figure 2. the values of the resistor divider can be selected so that the en/uvlo pin voltage exceeds the 1.21v (typical) turn on threshold at the desired input dc bus voltage. the same resistor divider can be modified with an additional resistor, r ovi , to implement input over - voltage protection, in addition to the en/uvlo functional - ity as shown in figure 2. when the voltage at the ovi pin exceeds 1.21v (typical), the MAX17598/max17599 stop switching. switching resumes with soft-start operation, only if the voltage at the ovi pin falls below 1.15v (typi - cal). the ovi feature is easily disabled by tying the pin to ground. for given values of startup dc input voltage (v start ) and input overvoltage protection voltage (v ovi ), the resistor values for the divider can be calculated as follows, assuming a 24.9k i resistor for r ovi . r sum rep - resents the series combination of several resistors that might be needed in high-voltage dc bus applications (MAX17598) or a single resistor in low-voltage dc-dc applications (max17599). ovi en start v r 24.9 1 k , v ?? = ?w ?? ?? where v start and v ovi are in volts. [ ] start sum en v r 24.9 r 1 k , 1.21 ?? = + ?w ?? ?? where r en is in k i . r sum might need to be implemented as equal multiple resistors in series (rdc1, rdc2, rdc3) so that voltage across each resistor is limited to its maximum operating voltage. sum dc1 dc1 dc1 r rrr k. 3 = = = w MAX17598 max17599 r dc 1 r dc 2 r dc 3 r sum en /u vlo ovi r en r ovi v dc
???????????????????????????????????????????????????????????????? maxim integrated products 15 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers startup operation the MAX17598 is optimized for implementing active- clamp converters operating either from a rectified ac input or in a 36v dc to 72vdc telecom application. a cost-effective rc startup circuit can be used in such applications. in this startup method (figure 3), when the input dc voltage is applied, the startup resistor r start charges the startup capacitor c start , causing the voltage at the v in pin to increase towards the rising v in uvlo threshold (20v typical). during this time, the MAX17598 draws a low startup current of 20 f a (typical) through the startup resistor r start . when the voltage at v in reaches the rising in uvlo threshold, the MAX17598 commences switching operations and drives the exter - nal mosfets connected to ndrv and auxdrv. in this condition, the MAX17598 draws 2.5ma (typical) current in from c start , in addition to the current required to switch the gates of the external mosfets q1and q2. since this current cannot be supported by the current through r start , the voltage on c start starts to drop. when suitably configured as shown in figure 3, the con - verter operates to generate an output voltage (v bias ) that is bootstrapped to the v in pin. if the voltage v bias exceeds 8v before the voltage on c start falls below 8v, then the v in voltage is sustained by v bias , thus allow - ing the MAX17598 to continue to operate with energy from v bias . the large hysteresis (13v typical) of the MAX17598 allows for a small startup capacitor (c start ). the low startup current (20 f a typical) allows the use of a large startup resistor (r start ), thus reducing power dissipation at higher dc bus voltages. the startup resis - tor r start might need to be implemented as equal, mul - tiple resistors in series (r in1 , r in2 and r in3 ) to share the applied high dc voltage in offline applications so that the voltage across each resistor is limited to the maximum continuous operating voltage rating. r start and c start can be calculated as follows: gate sw ss start in 6 q ft c i f 10 10 ?? ?? = + ?? ?? ?? ?? where i in is the supply current drawn at the in pin in ma, q gate is the sum of the gate charges of the external mosfets q1 and q2 in nc, f sw is the switching frequen - cy of the converter in hz, and t ss is the soft-start time programmed for the converter in ms. see the soft-start section. ( ) start start start v 10 50 r k, 1c ? = w + ?? ?? where c start is the startup capacitor in f f. the in uvlo rising threshold of the max17599 is set to 4.1v with a hysteresis of 200mv, and is optimized for low-voltage dc-dc applications in the range of 4.5v dc to 36v dc. the in pin is rated for a maximum operating input voltage of 36v dc and can directly be connected to the input dc supply. figure 3. rc-based startup circuit r in1 r in2 r in3 ldo v in v dc v bias d1 d2 l bias c clamp auxdrv v dc auxdrv ndrv q1 q2 v drv c vdrv c start r start MAX17598
???????????????????????????????????????????????????????????????? maxim integrated products 16 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers soft-start and soft-stop in a current-mode isolated active clamp forward con - verter, the comp voltage programs the peak current in the primary, and thus the secondary-side inductor current as well. the MAX17598/max17599 implement a soft-start scheme that controls the comp pin of the device at turn on. a useful benefit of this feature is the elimination of need for secondary-side soft-start circuitry in such isolated applications. in the absence of sec - ondary-side soft-start circuitry, the secondary-side error amplifier can drive the optocoupler with large currents to cause the output voltage to rapidly reach the regulation value, thus causing inrush current and output voltage overshoot. the MAX17598/max17599 avoid this issue by applying a soft-start to the comp pin. thus the regu - lators primary and secondary currents are ramped up in a well-controlled manner resulting in a current-mode soft-start operation. the soft-start period of the MAX17598/max17599 can be programmed by selecting the value of the capacitor connected from the ss pin to gnd. the capacitor c ss can be calculated as follows: ss ss comp ss ss t .i v c v 2.6 = where i ss = 10 f a, v ss = 1.23v, v comp is steady-state comp voltage. a soft-stop feature ramps down the output voltage when the device is turned off, and provides safe discharging of the clamp capacitor, thus allowing the controller to restart in a well-controlled manner. additionally, a nega - tive current limit is provided in the current-sense circuitry that helps limit the clamp switch current under dynamic operating conditions, such as momentary input overvolt - age charging into a precharged output capacitor. the soft-stop duration is twice that of the programmed soft- start period. programming slope compensation since the MAX17598/max17599 operate at a maximum duty cycle of 70%, slope compensation is required to prevent subharmonic instability that occurs naturally in continuous mode, peak current mode-controlled con - verters operating at duty cycles greater than 50%. a minimum amount of slope signal is added to the sensed current signal, even for converters operating below 50% duty to provide stable, jitter-free operation. the slope pin allows the user to program the necessary slope compensation by setting the value of the resistor r slope connected from slope pin to ground. e slope s8 rk 1.55 ? = w where s e , the slope is expressed in mv per microseconds. for the default minimum slope compensation of 50mv/ f s (typical), the slope pin should be connected to sgnd or left unconnected. figure 4. typical startup circuit with in connected directly to dc input max17599 ldo v in 4.5v to 36v dc v out d1 d2 l out c clamp auxdrv auxdrv ndrv q1 q2 v drv c vdrv c out
???????????????????????????????????????????????????????????????? maxim integrated products 17 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers figure 5. duty cycle soft-start figure 6. duty cycle or current soft-stop auxdrv cs soft-start begi n 0.0v 0.4v ndrv v ss = i ssch x t/ c ss v comp - 1.36v soft-start ends soft-stop ends 0.4v 0.0v v comp - 1.36 v soft-stop begins v ss = 1.23v - i ssdisc h x t/ c ss auxdrv cs ndrv
???????????????????????????????????????????????????????????????? maxim integrated products 18 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers n-channel mosfet gate driver the ndrv output drives an external n-channel mosfet. ndrv can source/sink in excess of 900ma /1500ma peak current. therefore, select a mosfet that yields acceptable conduction and switching losses. p-channel mosfet gate driver the auxdrv output drives an external p-channel mosfet with the aid of a level shifter, as shown in the typical application circuits . auxdrv can source/sink in excess of 300ma/600ma peak current. therefore, select a mosfet that yields acceptable conduction and switch - ing losses. the external pmosfet used must be able to withstand the maximum clamp voltage. dead time dead time between the main and aux output edges allow zvs to occur, minimizing switching losses and improving efficiency. the dead time (t dt ) is applied to both leading and trailing edges of the main and aux outputs as shown in figure 7. connect a resistor between dt and gnd to set t dt to any value between 25ns and 250ns: dt dt 10k r (t ) 25ns w = oscillator/switching frequency the ics switching frequency is programmable between 100khz and 1mhz with a resistor r rt connected between rt and gnd. use the following formula to determine the appropriate value of r rt needed to generate the desired output switching frequency (f sw ): 10 rt sw 1 10 r f = where f sw is the desired switching frequency. peak-current-limit the current-sense resistor ( r cs ), connected between the source of the n-channel mosfet and pgnd, sets the current limit. the source end of the current-sense resis - tor connects to the cs pin of the MAX17598/max17599. the signal thus obtained is used by the devices, both for current-mode control and peak-current limiting purposes. the current-limit comparator has a voltage trip level (v cs-peak ) of 300mv, and is independent of slope compensation applied to stabilize the converter. the following equation is used to calculate the value of r cs : cs pri_peak 300mv r 1.2 i = where i pri_peak is the peak current in the primary side of the transformer, which also flows through the main n-channel mosfet. when the voltage produced by this current (through the current-sense resistor) exceeds the current-limit comparator threshold, the mosfet driver (ndrv) terminates the current on-cycle within 40ns (typ). the devices implement 70ns of internal leading-edge blanking to ignore leading-edge current spikes encoun - tered in practice due to parasitics. use a small rc network for additional filtering of the leading-edge spike on the sense waveform when needed. set the corner frequency of the rc filter network at 5 to 10 times the switching frequency. for a given peak-current-limit setting, the runaway cur - rent limit is typically 20% higher. the peak current-limit- triggered hiccup operation is disabled until the end of soft-start, while the runaway current-limit-triggered hiccup operation is always enabled. negative peak current limit the MAX17598/max17599 protect against excessive negative currents through the clamp switch, primary of the transformer and the clamp capacitor under dynamic operating conditions where the converter is not in steady state. the devices limit negative current by monitoring the voltage across r cs , while the auxdrv output is low and the p-channel fet is on. the typical negative-cur - rent-limit threshold is set at -100mv (1/3 of the positive- peak-current-limit threshold). figure 7. dead time between auxdrv and ndrv auxdrv ndrv dead time, t dt
???????????????????????????????????????????????????????????????? maxim integrated products 19 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers output short-circuit protection with hiccup mode when the MAX17598/max17599 detect eight consecu - tive peak-current-limit events, both ndrv and auxdrv driver outputs are turned off (hiccup is followed by soft-stop) for a restart period, trstrt. after trstrt, the device turns on again with a soft-start. the duration of the restart period is 32678 clock cycles, and therefore depends on the switching frequency setting. the device also features a runaway current limit setting at 120% (typi - cal) of the peak current limit. this feature is useful under short-circuit faults in forward converters with synchronous rectifiers that occur during minimum on-time conditions at high input voltages. under these conditions, the primary peak current tends to build up and staircase beyond the peak current limit setting due to insufficient discharging of the output inductor. one single event of a runaway current limit forces the MAX17598/max17599 into hiccup mode operation. figure 8 shows the behavior of the device prior and during hiccup mode. oscillator synchronization the internal oscillator can be synchronized to an external clock by applying the clock to sync/dither directly. the external clock frequency can be set anywhere between 1.1x to 1.3x the internal clock frequency. using an external clock increases the maximum duty cycle by a factor equal to f sync /f sw . frequency dithering for spread-spectrum applications (low emi) the switching frequency of the converter can be dith - ered in a range of q 10% by connecting a capacitor from dither/sync to gnd, and a resistor from dither to rt as shown in the typical applications circuit . this results in lower emi. figure 8. hiccup-mode timing diagram current-sense voltage hiccup signal soft-start voltage, v ss v ss-h i hiccup timeou t t ss t rstr discharge with issdisch v cs-peak (300mv)
???????????????????????????????????????????????????????????????? maxim integrated products 20 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers a current source at sync/dither charges the capacitor cdither to 2v at 50 f a. upon reaching this trip point, it discharges cdither to 0.4v at 50 f a. the charging and discharging of the capacitor generates a triangular waveform on sync/dither with peak levels at 0.4v and 2v and a frequency that is equal to: tri dither 50 a f c 3.2v = typically, f tri should be set close to 1khz. the resistor r dither connected from sync/dither to rt deter - mines the amount of dither as follows: rt dither r %dither r = where %dither is the amount of dither expressed as a percentage of the switching frequency. setting r dither to 10 x r rt generates q 10% dither. error amplifier and loop compensation the MAX17598/max17599 include an internal transcon - ductance-type error amplifier. the noninverting input of the error amplifier is internally connected to the internal reference and the inverting input is brought out at the fb pin to apply the feedback signal. the internal reference is 1.23v (typical) when the device is enabled at turn on. in isolated applications, where an optocoupler is used to transmit the error signal from the secondary side, the emitter current of the optocoupler flows through a resis - tor to ground to set-up the feedback voltage. a shunt regulator is usually employed as a secondary-side error amplifier to drive the optocoupler photo-diode to couple the error signal to the primary. the loop compensation is usually applied in the secondary side as an r-c network on the shunt regulator. the MAX17598/max17599 error amp is set-up as a proportional gain amplifier. this is demonstrated in the typical application circuit for the MAX17598/max17599. a useful feature of the MAX17598 is the elimination of need for secondary-side soft-start circuitry. in the absence of secondary side soft-start circuitry, the secondary side error amplifier can drive the optocoupler with large currents to cause the output voltage to rapidly reach the regulation value, thus causing inrush current and output voltage overshoot. the MAX17598/max17599 avoid this issue by applying a soft-start to the comp pin. the regu - lators primary and secondary currents are ramped up in a well-controlled manner, resulting in a current soft-start operation. in nonisolated applications, the output voltage is divided down with a voltage divider to ground and is applied to the fb pin. loop compensation is applied at the comp pin as an r-c network from comp to gnd that imple - ments the required poles and zeros, as shown in figure 9. active-clamp circuit design the external n-channel and p-channel mosfets used must be able to withstand the maximum clamp voltage. for a continuous-mode conduction converter, the clamp voltage is a function of operating duty cycle d and input voltage. the maximum clamp voltage can be obtained as the greater of the results obtained by the following expressions: ( ) 2 in_max clamp_max in_max in_min clamp_max in_min v v or v 0.7 v v 3.33 v , = ?? ? ?? = where v in_max is the maximum operating dc input volt - age, and v in_min is the minimum operating dc input voltage. figure 9. programming output voltage non-isolated applications comp c z r z v out fb r u r b c p MAX17598 max17599
???????????????????????????????????????????????????????????????? maxim integrated products 21 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers the aux driver controls the p-channel fet through a level shifter. the level shifter consists of an rc network (formed by c 8 and r 11 ) and diode d4, as shown in the typical applications circuits . choose r and c so that the time constant exceeds 100 x f sw . diode d4 is a small- signal diode with a voltage rating exceeding 25v. additionally, c clamp should be chosen so that the com - plex poles formed by the transformers primary magnetiz - ing inductance (lmag) and c clamp are 5x away from the loop bandwidth, and 8x to 10x below the switching frequency of the converter. this allows the clamp capaci - tor voltage to reach steady-state conditions quickly when subjected to transients in load and line and to avoid transformer saturation. bw sw mag clamp 1-d 5 f 0.1 f 2l c < < layout recommendations all connections carrying pulsed currents must be very short and as wide as possible. the inductance of these connections must be kept to an absolute minimum due to the high di/dt of the currents in high-frequency switch - ing power converters. this implies that the loop areas for forward- and return-pulsed currents in various parts of the circuit should be minimized. additionally, small current loop areas reduce radiated emi. similarly, the heatsink of the mosfet presents a dv/dt source. therefore, the sur - face area of the mosfet heatsink should be minimized as much as possible. ground planes must be kept as intact as possible. the ground plane for the power section of the converter should be kept separate from the analog ground plane, except for a connection at the least-noisy section of the power ground plane, typically the return of the input filter capacitor. the negative terminal of the filter capacitor, the ground return of the power switch, and current-sensing resistor must be close together. pcb layout also affects the thermal performance of the design. a number of ther - mal vias that connect to a large ground plane should be provided under the exposed pad of the part for efficient heat dissipation. for a sample layout that ensures first pass success, please refer to the MAX17598/max17599 evaluation kit layouts available at www.maxim-ic.com . for universal ac input designs, follow all applicable safety regulations. offline power supplies can require ul, vde, and other similar agency approvals.
???????????????????????????????????????????????????????????????? maxim integrated products 22 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers typical application circuits figure 10. typical application circuit (telecom power supplies) q3 q4 r16 200mi c9 330pf c10 2.2f auxdrv ss slope sgnd v bias v bias v in d2 d1 c2 0.022f c1 22f c5 0.022f 16v l2 4.7f l1 1000h pgnd input v out gnd 36v to 72v input v drv r3 50ki ovi sgnd sgnd en / uvlo r2 84ki r1 3.1mi r4 80ki r5 30ki r6 open c4 short c3 68nf r9 10ki r17 0i r11 0i r12 0i c12 100f c13 22f c14 open en / uvlo ovi v in sgnd pgnd r16 20ki dt sgnd pgnd ep v drv cs c8 0.047f c7 2.2f 36v c11 0.01f ndrv pgnd sgnd pgnd gnd0 pgnd sgnd rt r7 10ki r8 6ki comp fb dither / sync sgnd r13 10ki d4 3.3v, 10 a output r14 100i t1 v out v fb pgnd q1 q2 r20 100i r21 open r22 5ki r23 84ki r24 50ki r19 1.2ki tlv431 v fb v drv v out c16 22nf c16 330pf u2 1 2 3 u3 sgnd gnd0 r18 0i v in u1 MAX17598 c6 0.47f pgnd
???????????????????????????????????????????????????????????????? maxim integrated products 23 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers typical application circuits (continued) q2 q1 r15 100mi c8 330pf c9 2.2f auxdrv ss slope sgnd c2 0.1f 50v c1 22f 75v l2 22f pgnd input v out gnd0 10v to 30v input v drv r3 50ki ovi sgnd en / uvlo r2 109ki r1 1.14mi r4 20ki r5 30ki r10 0i r6 open c4 short c3 68nf r11 0i r12 0i c11 10f 16v c12 10f 16v en / uvlo ovi v in sgnd pgnd r16 20ki dt ep v drv cs c7 0.01f c10 0.01f ndrv pgnd sgnd pgnd gnd0 sgnd rt r9 15ki r8 10ki comp fb v fb dither / sync sgnd r13 10ki d4 5v, 2a output r14 100i t1 v out q4 q3 r20 511i r21 open r22 5ki r23 151.6ki r24 50ki r19 1.2ki tlv431 v fb v drv v out c14 100nf c15 330pf u2 1 2 3 u3 sgnd pgnd gnd0 r18 0i v in u1 max17599 c6 0.47f pgnd r17 0i 4 5 2 1 6 sgnd sgnd sgnd pgnd
???????????????????????????????????????????????????????????????? maxim integrated products 24 MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers ordering information + denotes a lead(pb)-free/rohs-compliant package. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin package functionality uvlo, in clamp dmax MAX17598 ate+ -40 n c to +125 n c 16 tqfn active clamp, peak current mode, offline pwm controller 20v, yes 70% max17599 ate+ -40 n c to +125 n c 16 tqfn active clamp, peak current mode, pwm dc-dc controller 4v, no 70% package type package code outline no. land pattern no. 16l tqfn t1633+4 21-0136 90-0032
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 25 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/12 initial release MAX17598/max17599 low i q , wide-input range, active clamp current-mode pwm controllers

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